This invention is directed to semiconductor memories and to methods of making such devices, and more particularly to static Random Access Memories implemented in MOS integrated circuits.
In early semiconductor integrated circuits, resistors were provided by diffused regions or by portions of the semiconductor substrate which were defined by etching, as seen in U.S. Pat. No. 3,138,743, issued to Jack S. Kilby. As the density of components grew, the area occupied by resistors became prohibitive, so logic forms were favored which used few resistors or no resistors. For example, "TTL" or Transistor-Transistor Logic, and I.sup.2 L for integrated injection logic in bipolar technology had features minimizing the area on a bar dedicated to resistors. In MOS logic and memories, transistors are used as load devices or, in effect, as resistors. Examples of very complex MOS circuits containing many thousands of transistors, but no resistors, in a single chip digital processor or memory are shown in U.S. Pat. No. 3,940,747, issued to Kuo and Kitagawa and U.S. Pat. No. 3,998,604, issued to J.H. Raymond, Jr..
High density MOS memory devices such as the 4096 bit memory described in U.S. Pat. No. 3,940,747, or the "16K" or 16384 bit memory described in U.S. Pat. No. 4,031,415 by N. Kitagawa, have been of the dynamic type because dynamic 1-transistor cells are the smallest in area. In some parts of digital equipment, however, the refresh circuitry required for dynamic memories is incompatible or undesirable, so static memory is preferred. Static cells traditionally employ 6-transistor bistable circuits wherein depletion-load MOS transistors are used as load devices. These cells are much larger than the one transistor cells of dynamic memory devices, so accordingly the density is less. Also, power dissipation is high due to the requirement that some current must flow through one side of each cell in the array to maintain the stored data. In co-pending Application Ser. No. 691,252, filed May 28, 1976 by G. R. Mohan Rao, assigned to Texas Instruments, there is disclosed a resistor element particularly suited for a static RAM cell wherein the resistors are implanted regions buried beneath field oxide. In U.S. Pat. No. 4,110,776, by Rao, Stanczak, Lien, and Bhatia, a static cell using implanted resistors in a polycrystalline silicon over field oxide is described. In co-pending Application, Ser. No. 048,961, filed June 15, 1979, by Jih-Chang Lien and Te-Lang Chiu, assigned to Texas Instruments, a static cell, using resistors imiplanted in second-level polycrystalline silicon is disclosed. While these inventions represent marked improvements, further reduction in cell size is needed for arrays of the "16K" or larger size.
It is therefore, a principal object of this invention, to provide a method for making an improved small area static RAM cell for MOS memory devices of high density. Another object of this invention is to provide small area, high resistance load elements for use in a small area static RAM cell.